This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits may be configured as memory circuits to store and access data. Some integrated circuits include circuitry to perform monitoring functions to assist with detecting whether a power supply has reached safe levels. Sometimes, integrated circuits are subject to current surges, and protection may be achieved with a type of circuit known as a power-on-reset (POR) circuit.
FIG. 1 shows a diagram of a conventional POR circuit 100 having a resistor-capacitor (RC) circuit 110 and a delay circuit 112. The RC circuit 110 typically includes a resistor R and a capacitor C arranged to provide an RC signal at an output node N, and the delay circuit 112 typically includes multiple inventers arranged in series to provide a delay stage to the RC signal. In this circuit 100, the delayed output signal may be referred to as a POR reset signal or reset pulse signal.
Unfortunately, this conventional POR circuit 100 is deficient. For instance, to have a high pulse that is sufficient to latch correctly, the size of the resistor R and capacitor C in the RC circuit should be substantially large, and hence, deficiencies can arise in a high cost of area. Further, the delay circuit 112 typically suffers from variability and also uses a large area to provide a substantial delay at slow supply ramp. As such, implementation of a substantially large circuit is not a viable solution in some cases, and the conventional approach is susceptible to failure with device variations. Further, in some situations, the conventional approach is not robust enough to generate reset under PVT (pressure, voltage, and temperature) variations.